MIPSim software simulador da microarquitetura MIPS de processador multi-ciclos

Abstract

This paper presents the development and implementation of MIPSim, a simulator of the MIPS microarchitecture of a multi-cycle processor. The main objective of this project is to create an educational tool that helps students and researchers understand and analyze the internal operations of a MIPS processor, specifically in the multi-cycle configuration. Initially, the fundamental concepts of the MIPS architecture were reviewed, highlighting its characteristics and operation. Next, the microarchitecture of a multi-cycle processor was detailed, explaining how instructions are processed in distinct stages. Then, the development of the simulator and its class architecture and other aspects were explained. Finally, the results were presented and discussed. MIPSim was developed using the JAVA programming language and the ControlsFX and JMetro packages. The JAVA language was chosen because it is a popular language in academia, and because it is an object-oriented language that is more familiar when it comes to structuring classes. The simulator allows users to visualize the instruction execution cycle and their respective states of the FSM (Finite State Machine), and can view data in memory segments, in the register set and in internal modules in real time. The aim is to demonstrate, using a sequential and parallel approach, how the interaction between the different components of the microprocessor works. The results obtained using MIPSim suggest its potential effectiveness as a teaching tool, providing a detailed view of the internal functioning of the multi-cycle processor. In addition, the simulator offers an interactive environment where users can experiment with different graphic elements and effects for greater accessibility. It is concluded that MIPSim is a valuable contribution to the teaching of computer architecture, facilitating learning and promoting a better understanding of the complex concepts involved in the execution of instructions in multi-cycle processors.